University of Hertfordshire

A 12-bit 150-MHz 1.25-mm2 CMOS DAC

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

A 12-bit 150-MHz 1.25-mm2 CMOS DAC. / He, Y.; Jiang, J.; Sun, Y.

Procs of the 2004 IEEE Region 10 Conference, TENCON. Vol. 4 IEEE, 2004. p. 237-240.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

He, Y, Jiang, J & Sun, Y 2004, A 12-bit 150-MHz 1.25-mm2 CMOS DAC. in Procs of the 2004 IEEE Region 10 Conference, TENCON. vol. 4, IEEE, pp. 237-240. https://doi.org/10.1109/TENCON.2004.1414913

APA

He, Y., Jiang, J., & Sun, Y. (2004). A 12-bit 150-MHz 1.25-mm2 CMOS DAC. In Procs of the 2004 IEEE Region 10 Conference, TENCON (Vol. 4, pp. 237-240). IEEE. https://doi.org/10.1109/TENCON.2004.1414913

Vancouver

He Y, Jiang J, Sun Y. A 12-bit 150-MHz 1.25-mm2 CMOS DAC. In Procs of the 2004 IEEE Region 10 Conference, TENCON. Vol. 4. IEEE. 2004. p. 237-240 https://doi.org/10.1109/TENCON.2004.1414913

Author

He, Y. ; Jiang, J. ; Sun, Y. / A 12-bit 150-MHz 1.25-mm2 CMOS DAC. Procs of the 2004 IEEE Region 10 Conference, TENCON. Vol. 4 IEEE, 2004. pp. 237-240

Bibtex

@inproceedings{e5ab03ef06894946b53a7ad55b0c1ae8,
title = "A 12-bit 150-MHz 1.25-mm2 CMOS DAC",
abstract = "This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ±0.6 LSB and ±0.9 LSB, respectively. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process. It occupies 1.27 mm×0.96 mm chip area, when operating at 150 MHz and dissipates 91.6 mW from a 5.0 V power supply, which is much smaller.",
author = "Y. He and J. Jiang and Y. Sun",
note = "“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"} “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”",
year = "2004",
doi = "10.1109/TENCON.2004.1414913",
language = "English",
isbn = "0-7803-8560-8",
volume = "4",
pages = "237--240",
booktitle = "Procs of the 2004 IEEE Region 10 Conference, TENCON",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - A 12-bit 150-MHz 1.25-mm2 CMOS DAC

AU - He, Y.

AU - Jiang, J.

AU - Sun, Y.

N1 - “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”

PY - 2004

Y1 - 2004

N2 - This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ±0.6 LSB and ±0.9 LSB, respectively. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process. It occupies 1.27 mm×0.96 mm chip area, when operating at 150 MHz and dissipates 91.6 mW from a 5.0 V power supply, which is much smaller.

AB - This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ±0.6 LSB and ±0.9 LSB, respectively. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process. It occupies 1.27 mm×0.96 mm chip area, when operating at 150 MHz and dissipates 91.6 mW from a 5.0 V power supply, which is much smaller.

U2 - 10.1109/TENCON.2004.1414913

DO - 10.1109/TENCON.2004.1414913

M3 - Conference contribution

SN - 0-7803-8560-8

VL - 4

SP - 237

EP - 240

BT - Procs of the 2004 IEEE Region 10 Conference, TENCON

PB - IEEE

ER -