University of Hertfordshire

A 54.4-mW 4th-order quadrature bandpass CT ΣΔ modulator with 33-MHz BW and 10-bit ENOB for a GNSS receiver

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages343-346
Number of pages4
Volume2015-November
ISBN (Electronic)9781479976416
DOIs
Publication statusPublished - 25 Nov 2015
EventIEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 - Phoenix, United States
Duration: 17 May 201519 May 2015

Conference

ConferenceIEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015
CountryUnited States
CityPhoenix
Period17/05/1519/05/15

Abstract

A 4th-order quadrature bandpass continuous-time sigma-delta modulator for a GNSS receiver is presented. With significantly wide bandwidth, the modulator is able to digitalize the down-conversed GNSS signals in two adjacent signal bands simultaneously. This makes it possible to realize simultaneous dual-frequency reception from two satellite systems with one receiver channel instead of two independent channels. A direct RZ feedback is introduced into the input of the last integrator to realize ELD compensation. Power-efficient amplifiers are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-bit quantizers. Implemented in 180nm CMOS, the modulator achieves 62.1dB peak SNDR, 64dB DR and 59.3dB image rejection ratio (IRR), and consumes 54.4mW from a 1.8V power supply.

ID: 15579630