University of Hertfordshire

A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationISCAS 2016
Place of PublicationMontreal Cananda
PublisherIEEE
Pages1950-1953
Number of pages4
ISBN (Electronic)978-1-4799-5341-7
ISBN (Print)978-1-4799-5342-4
DOIs
Publication statusPublished - 11 Aug 2016
EventInternational Symposium on Circuits and Systems (ISCAS) - Montreal , Canada
Duration: 22 May 201625 May 2016
http://iscas2016.org/

Conference

ConferenceInternational Symposium on Circuits and Systems (ISCAS)
Abbreviated titleISCAS 2016
CountryCanada
CityMontreal
Period22/05/1625/05/16
Internet address

Abstract

In this paper a novel simple all digital frequency locking circuit design is presented together with its performance results. The proposed method can be used to lock DDSs to a reference clock such as a data clock. It allows for efficient fully multi-rate modem design (with a resolution bound by the DDS) within a low cost FPGA. In fact, using the new scheme the baseband modem can be completely constructed within the FPGA without external complicated and expensive VCOs and their associated locking loops.

Notes

© 2016 IEEE

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