University of Hertfordshire

By the same authors

A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip. / Karavadara, Nilesh; Folie, Simon; Zolda, Michael; Nguyen, Vu Thien Nga; Kirner, Raimund.

Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14). 2014.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Karavadara, N, Folie, S, Zolda, M, Nguyen, VTN & Kirner, R 2014, A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip. in Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14). Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems , Dresden, Germany, 24/03/14.

APA

Karavadara, N., Folie, S., Zolda, M., Nguyen, V. T. N., & Kirner, R. (2014). A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip. In Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)

Vancouver

Karavadara N, Folie S, Zolda M, Nguyen VTN, Kirner R. A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip. In Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14). 2014

Author

Karavadara, Nilesh ; Folie, Simon ; Zolda, Michael ; Nguyen, Vu Thien Nga ; Kirner, Raimund. / A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip. Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14). 2014.

Bibtex

@inproceedings{c400411849424dcfb75b42ccdb206f24,
title = "A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip",
abstract = "Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores.Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network.We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices.Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.",
author = "Nilesh Karavadara and Simon Folie and Michael Zolda and Nguyen, {Vu Thien Nga} and Raimund Kirner",
note = "Nilesh Karavadara, Simon Folie, Michael Zolda, Vu Thien Nga Nguyen, Raimund Kirner, 'A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip'. Paper presented at the Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14), Dresden, Germany, 24-28 March 2014.",
year = "2014",
month = "3",
day = "1",
language = "English",
booktitle = "Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)",

}

RIS

TY - GEN

T1 - A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

AU - Karavadara, Nilesh

AU - Folie, Simon

AU - Zolda, Michael

AU - Nguyen, Vu Thien Nga

AU - Kirner, Raimund

N1 - Nilesh Karavadara, Simon Folie, Michael Zolda, Vu Thien Nga Nguyen, Raimund Kirner, 'A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip'. Paper presented at the Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14), Dresden, Germany, 24-28 March 2014.

PY - 2014/3/1

Y1 - 2014/3/1

N2 - Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores.Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network.We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices.Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.

AB - Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores.Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network.We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices.Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.

M3 - Conference contribution

BT - Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)

ER -