University of Hertfordshire

An evaluation of the iHARP multiple instruction issue processor

Research output: Book/ReportOther report

Standard

An evaluation of the iHARP multiple instruction issue processor. / Steven, F.L.; Steven, G.B.; Wang, L.

University of Hertfordshire, 1994. (UH Computer Science Technical Report; Vol. 179).

Research output: Book/ReportOther report

Harvard

Steven, FL, Steven, GB & Wang, L 1994, An evaluation of the iHARP multiple instruction issue processor. UH Computer Science Technical Report, vol. 179, University of Hertfordshire.

APA

Steven, F. L., Steven, G. B., & Wang, L. (1994). An evaluation of the iHARP multiple instruction issue processor. (UH Computer Science Technical Report; Vol. 179). University of Hertfordshire.

Vancouver

Steven FL, Steven GB, Wang L. An evaluation of the iHARP multiple instruction issue processor. University of Hertfordshire, 1994. (UH Computer Science Technical Report).

Author

Steven, F.L. ; Steven, G.B. ; Wang, L. / An evaluation of the iHARP multiple instruction issue processor. University of Hertfordshire, 1994. (UH Computer Science Technical Report).

Bibtex

@book{cf1565d146904e83b51a596dc6090189,
title = "An evaluation of the iHARP multiple instruction issue processor",
abstract = "RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue multiple instructions in each processor cycle. This paper evaluates the architectural features of iHARP, a VLIW (Very Long Instruction Word) processor with an instruction issue rate of four, which has been developed at the University of Hertfordshire. One of the distinctive features of iHARP is the provision of Boolean guards on all instructions. Every iHARP instruction is only executed at run time if the attached Boolean guard is true. This paper evaluates the benefits of guarded instruction execution and quantifies its performance advantage. Other architectural features considered include instruction issue rate, code size, number of data cache ports, number of register file write ports, number of branch units and addressing mechanisms. The evaluation uses RLS, a resource limited instruction scheduler, specifically developed to statically reorder code for parallel execution on iHARP.",
keywords = "guarded instruction execution, instruction scheduling, superscalar",
author = "F.L. Steven and G.B. Steven and L. Wang",
year = "1994",
language = "English",
series = "UH Computer Science Technical Report",
publisher = "University of Hertfordshire",

}

RIS

TY - BOOK

T1 - An evaluation of the iHARP multiple instruction issue processor

AU - Steven, F.L.

AU - Steven, G.B.

AU - Wang, L.

PY - 1994

Y1 - 1994

N2 - RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue multiple instructions in each processor cycle. This paper evaluates the architectural features of iHARP, a VLIW (Very Long Instruction Word) processor with an instruction issue rate of four, which has been developed at the University of Hertfordshire. One of the distinctive features of iHARP is the provision of Boolean guards on all instructions. Every iHARP instruction is only executed at run time if the attached Boolean guard is true. This paper evaluates the benefits of guarded instruction execution and quantifies its performance advantage. Other architectural features considered include instruction issue rate, code size, number of data cache ports, number of register file write ports, number of branch units and addressing mechanisms. The evaluation uses RLS, a resource limited instruction scheduler, specifically developed to statically reorder code for parallel execution on iHARP.

AB - RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue multiple instructions in each processor cycle. This paper evaluates the architectural features of iHARP, a VLIW (Very Long Instruction Word) processor with an instruction issue rate of four, which has been developed at the University of Hertfordshire. One of the distinctive features of iHARP is the provision of Boolean guards on all instructions. Every iHARP instruction is only executed at run time if the attached Boolean guard is true. This paper evaluates the benefits of guarded instruction execution and quantifies its performance advantage. Other architectural features considered include instruction issue rate, code size, number of data cache ports, number of register file write ports, number of branch units and addressing mechanisms. The evaluation uses RLS, a resource limited instruction scheduler, specifically developed to statically reorder code for parallel execution on iHARP.

KW - guarded instruction execution

KW - instruction scheduling

KW - superscalar

M3 - Other report

T3 - UH Computer Science Technical Report

BT - An evaluation of the iHARP multiple instruction issue processor

PB - University of Hertfordshire

ER -