University of Hertfordshire

Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Documents

  • C. Egan
  • F.L. Steven
  • G.B. Steven
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Original languageEnglish
Title of host publicationIn: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf
PublisherIEEE
Pages266-271
ISBN (Print)0-8186-8215-9
Publication statusPublished - 1997

Abstract

While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling.

ID: 102650