University of Hertfordshire

Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    Final published version, 282 KB, PDF document

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Original languageEnglish
Title of host publicationProcs IEEE Int Symposium on Circuits & Systems
Subtitle of host publicationISCAS 2001
PublisherIEEE
Pages854-857
Volume4
ISBN (Print)0-7803-6685-9
DOIs
Publication statusPublished - 2001

Abstract

This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.

Notes

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