University of Hertfordshire

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Original languageEnglish
PublisherUniversity of Hertfordshire
Publication statusPublished - 1994

Publication series

NameUH Computer Science Technical Report
PublisherUniversity of Hertfordshire
Volume163

Abstract

This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in conjunction with a simple compile-time scheduling technique called conditional compaction. The architecture is characterised by a conditional execution mechanism which is used by the scheduler to pack the instructions within a procedure into long instruction words. The study compares the speedups obtained for the C and Modula-2 versions of a set of short, general purpose, integer benchmarks, running on simulations of the architecture with different functional unit configurations.

Notes

Submitted to 2nd Euromicro Workshop on Parallel and Distributed Processing, Spain, 1994

ID: 98648