University of Hertfordshire

From the same journal

Documents

  • Vasileios Tenentes
  • Daniele Rossi
  • Saqib Khursheed
  • Bashir M. Al-Hashimi
  • Krishnendu Chakrabarty
View graph of relations
Original languageEnglish
Number of pages13
Pages (from-to)883-895
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal publication date1 Apr 2018
Volume37
Issue4
Early online date19 Jul 2017
DOIs
Publication statusPublished - 1 Apr 2018

Abstract

Manufacturing defects that do not affect the functional operation of low power integrated circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS'05 benchmarks synthesized using a 32 nm CMOS technology, the tradeoffs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R 10 M (weak bridges) and bridges of R 10 M (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27 K and 157 K gate equivalents, respectively.

Notes

This document is the Accepted Manuscript version of the following article: Vasileios Tenentes, Daniele Rossi, Saqib Khursheed, Bashir M. Al-Hashimi, and Krishnendu Chakrabarty, ‘Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs’, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2017. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

ID: 12461546