University of Hertfordshire

By the same authors

Power droop reduction during Launch-On-Shift scan-based logic BIST

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • M. Omana
  • D. Rossi
  • E. Beniamino
  • C. Metra
  • C. Tirumurti
  • R. Galivanche
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Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages21-26
Number of pages6
ISBN (Electronic)9781479961559
DOIs
Publication statusPublished - 18 Nov 2014
Event27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, Netherlands
Duration: 1 Oct 20143 Oct 2014

Conference

Conference27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014
CountryNetherlands
CityAmsterdam
Period1/10/143/10/14

Abstract

The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.

ID: 13199204