University of Hertfordshire

Power droop reduction during Launch-On-Shift scan-based logic BIST

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

Power droop reduction during Launch-On-Shift scan-based logic BIST. / Omana, M.; Rossi, D.; Beniamino, E.; Metra, C.; Tirumurti, C.; Galivanche, R.

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. p. 21-26 6962063.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Omana, M, Rossi, D, Beniamino, E, Metra, C, Tirumurti, C & Galivanche, R 2014, Power droop reduction during Launch-On-Shift scan-based logic BIST. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 6962063, Institute of Electrical and Electronics Engineers Inc., pp. 21-26, 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, Netherlands, 1/10/14. https://doi.org/10.1109/DFT.2014.6962063

APA

Omana, M., Rossi, D., Beniamino, E., Metra, C., Tirumurti, C., & Galivanche, R. (2014). Power droop reduction during Launch-On-Shift scan-based logic BIST. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 21-26). [6962063] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2014.6962063

Vancouver

Omana M, Rossi D, Beniamino E, Metra C, Tirumurti C, Galivanche R. Power droop reduction during Launch-On-Shift scan-based logic BIST. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc. 2014. p. 21-26. 6962063 https://doi.org/10.1109/DFT.2014.6962063

Author

Omana, M. ; Rossi, D. ; Beniamino, E. ; Metra, C. ; Tirumurti, C. ; Galivanche, R. / Power droop reduction during Launch-On-Shift scan-based logic BIST. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 21-26

Bibtex

@inproceedings{de98b357f7ec4d68877ce3a915f69506,
title = "Power droop reduction during Launch-On-Shift scan-based logic BIST",
abstract = "The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50{\%} with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.",
keywords = "Logic BIST, Microprocessor, Power Droop, Test",
author = "M. Omana and D. Rossi and E. Beniamino and C. Metra and C. Tirumurti and R. Galivanche",
year = "2014",
month = "11",
day = "18",
doi = "10.1109/DFT.2014.6962063",
language = "English",
pages = "21--26",
booktitle = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

RIS

TY - GEN

T1 - Power droop reduction during Launch-On-Shift scan-based logic BIST

AU - Omana, M.

AU - Rossi, D.

AU - Beniamino, E.

AU - Metra, C.

AU - Tirumurti, C.

AU - Galivanche, R.

PY - 2014/11/18

Y1 - 2014/11/18

N2 - The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.

AB - The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.

KW - Logic BIST

KW - Microprocessor

KW - Power Droop

KW - Test

UR - http://www.scopus.com/inward/record.url?scp=84914706652&partnerID=8YFLogxK

U2 - 10.1109/DFT.2014.6962063

DO - 10.1109/DFT.2014.6962063

M3 - Conference contribution

SP - 21

EP - 26

BT - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

PB - Institute of Electrical and Electronics Engineers Inc.

ER -