A 12-bit 150-MHz 1.25-mm2 CMOS DAC

Y. He, J. Jiang, Y. Sun

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    Abstract

    This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ±0.6 LSB and ±0.9 LSB, respectively. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process. It occupies 1.27 mm×0.96 mm chip area, when operating at 150 MHz and dissipates 91.6 mW from a 5.0 V power supply, which is much smaller.
    Original languageEnglish
    Title of host publicationProcs of the 2004 IEEE Region 10 Conference, TENCON
    PublisherInstitute of Electrical and Electronics Engineers (IEEE)
    Pages237-240
    Volume4
    ISBN (Print)0-7803-8560-8
    DOIs
    Publication statusPublished - 2004

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