TY - JOUR
T1 - A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard
AU - He, Xiaofeng
AU - Zhu, Xi
AU - Duan, Lian
AU - Sun, Yichuang
AU - Ma, Chengyan
N1 - This is the accepted manuscript version of the following article: Xiaofeng He, et al., “A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61(10): 763-767, August 2014. The final published version is available at: http://ieeexplore.ieee.org/document/6871304/
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PY - 2014/10/1
Y1 - 2014/10/1
N2 - The design of a 14-mW receiver without phase-locked loop for the Chinese electronic toll collection (ETC) system in a standard 0.18-μm CMOS process is presented in this brief. Since the previously published work was mainly based on vehicle-powered systems, low power consumption was not the primary goal of such a system. In contrast, the presented system is designed for a battery-powered system. Utilizing the presented receiver architecture, the entire receiver only consumes 7.8 mA, at the supply voltage of 1.8 V, which indicates a power saving of at least 38% compared with other state-of-the-art designs for the same application. To verify the performance, the bit error rate is measured to be better than 10-6, which well satisfies the Chinese ETC standard. Moreover, the sensitivity of the designed receiver can be readjusted to -50 dBm, which is required by the standard.
AB - The design of a 14-mW receiver without phase-locked loop for the Chinese electronic toll collection (ETC) system in a standard 0.18-μm CMOS process is presented in this brief. Since the previously published work was mainly based on vehicle-powered systems, low power consumption was not the primary goal of such a system. In contrast, the presented system is designed for a battery-powered system. Utilizing the presented receiver architecture, the entire receiver only consumes 7.8 mA, at the supply voltage of 1.8 V, which indicates a power saving of at least 38% compared with other state-of-the-art designs for the same application. To verify the performance, the bit error rate is measured to be better than 10-6, which well satisfies the Chinese ETC standard. Moreover, the sensitivity of the designed receiver can be readjusted to -50 dBm, which is required by the standard.
KW - Amplitude-shift keying (ASK) demodulator
KW - Electronic toll collection (ETC)
KW - Intelligent transportation system (ITS)
UR - http://www.scopus.com/inward/record.url?scp=84907997815&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2014.2345303
DO - 10.1109/TCSII.2014.2345303
M3 - Article
AN - SCOPUS:84907997815
SN - 1549-7747
VL - 61
SP - 763
EP - 767
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 10
M1 - 2345303
ER -