Abstract
A 4th-order quadrature bandpass continuous-time sigma-delta modulator for a GNSS receiver is presented. With significantly wide bandwidth, the modulator is able to digitalize the down-conversed GNSS signals in two adjacent signal bands simultaneously. This makes it possible to realize simultaneous dual-frequency reception from two satellite systems with one receiver channel instead of two independent channels. A direct RZ feedback is introduced into the input of the last integrator to realize ELD compensation. Power-efficient amplifiers are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-bit quantizers. Implemented in 180nm CMOS, the modulator achieves 62.1dB peak SNDR, 64dB DR and 59.3dB image rejection ratio (IRR), and consumes 54.4mW from a 1.8V power supply.
Original language | English |
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Title of host publication | Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 343-346 |
Number of pages | 4 |
Volume | 2015-November |
ISBN (Electronic) | 9781479976416 |
DOIs | |
Publication status | Published - 25 Nov 2015 |
Event | IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 - Phoenix, United States Duration: 17 May 2015 → 19 May 2015 |
Conference
Conference | IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 |
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Country/Territory | United States |
City | Phoenix |
Period | 17/05/15 → 19/05/15 |
Keywords
- continuous-time
- power-efficient amplifier
- quadrature bandpass (complex bandpass)
- RZ ELD compensation
- sigma-delta modulator
- wide-band