A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter

X. Zhu; Y. Sun; J. Moritz

doi:10.1109/MWSCAS.2007.4488563

A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter

X. Zhu, Y. Sun, J. Moritz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

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Abstract

Read/write channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF). A 650 MHz current-mode seventh-order 0.05deg equiripple linear phase low-pass filter for computer hard disk read/write channels with data rates up to 1 Gbit/s is presented in this paper. It is implemented in CMOS using a leap-frog multiple loop feedback structure. The operational transconductance amplifier (OTA) used is based on a differential pair and uses source degeneration to achieve linearization and tuning. Simulated using a standard 0.18 mum CMOS process, the dynamic range at 1% THD of the filter is 48 dB, cut-off frequency can be tuned from 590 MHz to 690 MHz, group delay ripple is about 5%, and power consumption is 370 mW from supply voltage of 2.5 V.

Original language	English
Title of host publication	Procs 50th IEEE Int Midwest Symposium on Circuits & Systems
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	167-170
Volume	2007
ISBN (Print)	978-1-4244-1175-7
DOIs	https://doi.org/10.1109/MWSCAS.2007.4488563
Publication status	Published - 2007

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10.1109/MWSCAS.2007.4488563

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title = "A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter",

abstract = "Read/write channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF). A 650 MHz current-mode seventh-order 0.05deg equiripple linear phase low-pass filter for computer hard disk read/write channels with data rates up to 1 Gbit/s is presented in this paper. It is implemented in CMOS using a leap-frog multiple loop feedback structure. The operational transconductance amplifier (OTA) used is based on a differential pair and uses source degeneration to achieve linearization and tuning. Simulated using a standard 0.18 mum CMOS process, the dynamic range at 1% THD of the filter is 48 dB, cut-off frequency can be tuned from 590 MHz to 690 MHz, group delay ripple is about 5%, and power consumption is 370 mW from supply voltage of 2.5 V.",

author = "X. Zhu and Y. Sun and J. Moritz",

note = "“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"} “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”",

year = "2007",

doi = "10.1109/MWSCAS.2007.4488563",

language = "English",

isbn = "978-1-4244-1175-7",

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pages = "167--170",

booktitle = "Procs 50th IEEE Int Midwest Symposium on Circuits & Systems",

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AU - Zhu, X.

AU - Sun, Y.

AU - Moritz, J.

N1 - “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”

PY - 2007

Y1 - 2007

N2 - Read/write channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF). A 650 MHz current-mode seventh-order 0.05deg equiripple linear phase low-pass filter for computer hard disk read/write channels with data rates up to 1 Gbit/s is presented in this paper. It is implemented in CMOS using a leap-frog multiple loop feedback structure. The operational transconductance amplifier (OTA) used is based on a differential pair and uses source degeneration to achieve linearization and tuning. Simulated using a standard 0.18 mum CMOS process, the dynamic range at 1% THD of the filter is 48 dB, cut-off frequency can be tuned from 590 MHz to 690 MHz, group delay ripple is about 5%, and power consumption is 370 mW from supply voltage of 2.5 V.

AB - Read/write channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF). A 650 MHz current-mode seventh-order 0.05deg equiripple linear phase low-pass filter for computer hard disk read/write channels with data rates up to 1 Gbit/s is presented in this paper. It is implemented in CMOS using a leap-frog multiple loop feedback structure. The operational transconductance amplifier (OTA) used is based on a differential pair and uses source degeneration to achieve linearization and tuning. Simulated using a standard 0.18 mum CMOS process, the dynamic range at 1% THD of the filter is 48 dB, cut-off frequency can be tuned from 590 MHz to 690 MHz, group delay ripple is about 5%, and power consumption is 370 mW from supply voltage of 2.5 V.

U2 - 10.1109/MWSCAS.2007.4488563

DO - 10.1109/MWSCAS.2007.4488563

M3 - Conference contribution

SN - 978-1-4244-1175-7

VL - 2007

SP - 167

EP - 170

BT - Procs 50th IEEE Int Midwest Symposium on Circuits & Systems

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter

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