TY - JOUR
T1 - A Compositional Framework for Hardware/Software Co-Design
AU - . Cau, A
AU - Hale, R
AU - Dimitrov, J.
AU - Zedan, H.
AU - Moszkowski, B.
AU - Manjunathaiah, Manju
AU - Spivey, M.
N1 - © Kluwer Academic Publishers 2002
PY - 2002/7
Y1 - 2002/7
N2 - We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derivefrom a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.
AB - We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derivefrom a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.
U2 - 10.1023/A:1016507527035
DO - 10.1023/A:1016507527035
M3 - Article
SN - 0929-5585
VL - 6
SP - 367
EP - 399
JO - Design Automation for Embedded Systems
JF - Design Automation for Embedded Systems
IS - 4
ER -