A general framework for efficient FPGA implementation of matrix product

F. Bensaali, A. Amira, R. Sotudeh

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    Abstract

    High performance systems are required by the developers for fast processing of computationally intensive applications. Reconfigurable hardware devices in the form of Filed-Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in the construction of high performance systems at an economical price. Given the importance and the use of matrix algorithms in scientific computing applications, they seem ideal candidates to harness and exploit the advantages offered by FPGAs. In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customizable cores, designed for FPGA implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of two specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles while the second one is a parallel floating-point matrix multiplier designed for 3D affine transformations.
    Original languageEnglish
    Pages (from-to)124-131
    JournalMediterranean Journal of Computers and Networks
    Volume3
    Issue number3
    Publication statusPublished - 2007

    Keywords

    • matrix multiplication
    • field programmable gate array
    • distributed arithmetic
    • 3D affine transformations

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