Abstract
Reconfigurable systems have been proved to achieve significant performance speed-up by mapping the most time-consuming loops to a reconfigur- able units. Datapath merging (DPM) synthesis has identified the similarities among the Data Flow Graphs (DFGs) corresponding to the loops, and produces a single reconfigurable datapath that can be dynamically reconfigured to execute each DFG. This paper presents a new datapath merging method that produces a reconfigurable datapath with minimal area usage. At first it merges DFGs together one by one to create the reconfigurable datapath. Then it merges the functional units and interconnection units inside the reconfigurable datapath to reduce resource area usage. To do this, a new graph-based technique to merge the resources in the reconfigurable datapath is presented. We evaluate the proposed method using programs from the Media-bench benchmarks and experimental results show a decrease from 5% to 15% in reconfigurable data path resource area in comparison to previous algorithms.
Original language | English |
---|---|
Pages (from-to) | 157-168 |
Number of pages | 12 |
Journal | Lecture Notes in Computer Science (LNCS) |
Volume | 5453 |
DOIs | |
Publication status | Published - 2009 |
Externally published | Yes |
Event | 5th International Workshop of Applied Reconfigurable Computing, ARC 2009 - Karlsruhe, United States Duration: 16 Mar 2009 → 18 Mar 2009 |
Keywords
- Datapath merging
- High level synthesis
- Maximum weighted clique algorithm
- Reconfigurable computing