A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM

Andrew Slaney; Yichuang Sun; Oluyomi Simpson

doi:10.1109/ISCAS.2016.7538956

A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM

Andrew Slaney
, Yichuang Sun
, Oluyomi Simpson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper a novel simple all digital frequency locking circuit design is presented together with its performance results. The proposed method can be used to lock DDSs to a reference clock such as a data clock. It allows for efficient fully multi-rate modem design (with a resolution bound by the DDS) within a low cost FPGA. In fact, using the new scheme the baseband modem can be completely constructed within the FPGA without external complicated and expensive VCOs and their associated locking loops.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	ISCAS 2016
Place of Publication	Montreal Cananda
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1950-1953
Number of pages	4
ISBN (Electronic)	978-1-4799-5341-7
ISBN (Print)	978-1-4799-5342-4
DOIs	https://doi.org/10.1109/ISCAS.2016.7538956
Publication status	Published - 11 Aug 2016
Event	International Symposium on Circuits and Systems (ISCAS) - Montreal , Canada Duration: 22 May 2016 → 25 May 2016 http://iscas2016.org/

Conference

Conference	International Symposium on Circuits and Systems (ISCAS)
Abbreviated title	ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	22/05/16 → 25/05/16
Internet address	http://iscas2016.org/

Keywords

FPGA
Software Radio
MODEMs
Digital Frequency Locking Circuit Design
DSS

Access to Document

10.1109/ISCAS.2016.7538956Licence: Other

Cite this

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title = "A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM",

abstract = "In this paper a novel simple all digital frequency locking circuit design is presented together with its performance results. The proposed method can be used to lock DDSs to a reference clock such as a data clock. It allows for efficient fully multi-rate modem design (with a resolution bound by the DDS) within a low cost FPGA. In fact, using the new scheme the baseband modem can be completely constructed within the FPGA without external complicated and expensive VCOs and their associated locking loops.",

keywords = "FPGA, Software Radio, MODEMs, Digital Frequency Locking Circuit Design, DSS",

author = "Andrew Slaney and Yichuang Sun and Oluyomi Simpson",

note = "{\textcopyright} 2016 IEEE; International Symposium on Circuits and Systems (ISCAS), ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",

year = "2016",

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doi = "10.1109/ISCAS.2016.7538956",

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Slaney , A, Sun, Y & Simpson, O 2016, A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM. in IEEE International Symposium on Circuits and Systems : ISCAS 2016. Institute of Electrical and Electronics Engineers (IEEE), Montreal Cananda, pp. 1950-1953, International Symposium on Circuits and Systems (ISCAS), Montreal , Canada, 22/05/16. https://doi.org/10.1109/ISCAS.2016.7538956

A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM. / Slaney , Andrew; Sun, Yichuang ; Simpson, Oluyomi.
IEEE International Symposium on Circuits and Systems : ISCAS 2016. Montreal Cananda: Institute of Electrical and Electronics Engineers (IEEE), 2016. p. 1950-1953.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Sun, Yichuang

AU - Simpson, Oluyomi

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N2 - In this paper a novel simple all digital frequency locking circuit design is presented together with its performance results. The proposed method can be used to lock DDSs to a reference clock such as a data clock. It allows for efficient fully multi-rate modem design (with a resolution bound by the DDS) within a low cost FPGA. In fact, using the new scheme the baseband modem can be completely constructed within the FPGA without external complicated and expensive VCOs and their associated locking loops.

AB - In this paper a novel simple all digital frequency locking circuit design is presented together with its performance results. The proposed method can be used to lock DDSs to a reference clock such as a data clock. It allows for efficient fully multi-rate modem design (with a resolution bound by the DDS) within a low cost FPGA. In fact, using the new scheme the baseband modem can be completely constructed within the FPGA without external complicated and expensive VCOs and their associated locking loops.

KW - FPGA

KW - Software Radio

KW - MODEMs

KW - Digital Frequency Locking Circuit Design

KW - DSS

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DO - 10.1109/ISCAS.2016.7538956

M3 - Conference contribution

SN - 978-1-4799-5342-4

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EP - 1953

BT - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Montreal Cananda

T2 - International Symposium on Circuits and Systems (ISCAS)

Y2 - 22 May 2016 through 25 May 2016

ER -

A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM

Abstract

Conference

Keywords

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