TY - GEN
T1 - A Novel Low Power and High Speed 9-Transistors Dynamic Full-Adder Cell Simulation and Design
AU - Rahimi, Parisa
AU - Tabany, Myasar
AU - Pourmoafi, Seyedali
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - In this paper, a novel Full-Adder cell, named pseudo dynamic has been proposed and designed through an intensive simulation. The circuit has only 9 transistors and no internal nodes connected to ground. The circuit has been designed based on a 'floating full adder cell,' which has 3 inputs and a clock signal. Simulations have been performed using HSPICE 2008.03, based on 90nm technology, BSIM4 (level 54) version 4.4 model. The cell layout was designed and extracted by Tanner Research's L-Edit Version 13.00. Results show that the proposed new Full-Adder cell has considerable low power-delay product (PDP). The resulting PDP of a Multi-Output design with a 1.2 V power supply, 10 fF load capacitors, and a maximum input frequency of 200 MHz was 15.3405fJ. The maximum propagation delay was 25 pS, which shows the cell would work properly at high speeds.
AB - In this paper, a novel Full-Adder cell, named pseudo dynamic has been proposed and designed through an intensive simulation. The circuit has only 9 transistors and no internal nodes connected to ground. The circuit has been designed based on a 'floating full adder cell,' which has 3 inputs and a clock signal. Simulations have been performed using HSPICE 2008.03, based on 90nm technology, BSIM4 (level 54) version 4.4 model. The cell layout was designed and extracted by Tanner Research's L-Edit Version 13.00. Results show that the proposed new Full-Adder cell has considerable low power-delay product (PDP). The resulting PDP of a Multi-Output design with a 1.2 V power supply, 10 fF load capacitors, and a maximum input frequency of 200 MHz was 15.3405fJ. The maximum propagation delay was 25 pS, which shows the cell would work properly at high speeds.
KW - CMOS
KW - Floating Full-Adder
KW - Low Power
KW - Power-Delay Product
KW - Pseudo Dynamic Full Adder
UR - http://www.scopus.com/inward/record.url?scp=85171974688&partnerID=8YFLogxK
U2 - 10.1109/ISCC58397.2023.10217831
DO - 10.1109/ISCC58397.2023.10217831
M3 - Conference contribution
AN - SCOPUS:85171974688
T3 - Proceedings - IEEE Symposium on Computers and Communications
SP - 1287
EP - 1292
BT - ISCC 2023 - 28th IEEE Symposium on Computers and Communications
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 28th IEEE Symposium on Computers and Communications, ISCC 2023
Y2 - 9 July 2023 through 12 July 2023
ER -