@inproceedings{6a4d3c459a19473bb3fa8477dc3f10ec,
title = "A Novel Low Power and High Speed 9-Transistors Dynamic Full-Adder Cell Simulation and Design",
abstract = "In this paper, a novel Full-Adder cell, named pseudo dynamic has been proposed and designed through an intensive simulation. The circuit has only 9 transistors and no internal nodes connected to ground. The circuit has been designed based on a 'floating full adder cell,' which has 3 inputs and a clock signal. Simulations have been performed using HSPICE 2008.03, based on 90nm technology, BSIM4 (level 54) version 4.4 model. The cell layout was designed and extracted by Tanner Research's L-Edit Version 13.00. Results show that the proposed new Full-Adder cell has considerable low power-delay product (PDP). The resulting PDP of a Multi-Output design with a 1.2 V power supply, 10 fF load capacitors, and a maximum input frequency of 200 MHz was 15.3405fJ. The maximum propagation delay was 25 pS, which shows the cell would work properly at high speeds.",
keywords = "CMOS, Floating Full-Adder, Low Power, Power-Delay Product, Pseudo Dynamic Full Adder",
author = "Parisa Rahimi and Myasar Tabany and Seyedali Pourmoafi",
note = "{\textcopyright} 2023 IEEE.; 28th IEEE Symposium on Computers and Communications, ISCC 2023 ; Conference date: 09-07-2023 Through 12-07-2023",
year = "2023",
month = aug,
day = "28",
doi = "10.1109/ISCC58397.2023.10217831",
language = "English",
series = "Proceedings - IEEE Symposium on Computers and Communications",
publisher = "Institute of Electrical and Electronics Engineers (IEEE)",
pages = "1287--1292",
booktitle = "ISCC 2023 - 28th IEEE Symposium on Computers and Communications",
address = "United States",
}