A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs

Keyphrases

• Timing-driven 100%
• Configurable Logic Block 100%
• Routability 100%
• Multi-objective Optimization Algorithm 100%
• Device Utilization 50%
• Clustering Algorithm 25%
• Circuit Design 25%
• FPGA CAD 25%
• Performance Parameters 25%
• Place-and-route 25%
• Input Bandwidth 25%
• CAD Flow 25%
• Design Performance 25%
• In Clustering 25%
• Multi-objective Genetic Algorithm 25%
• Target Architecture 25%
• Block Utilization 25%
• Circuit Performance 25%
• Benchmark Circuits 25%
• EDA Flow 25%
• Clustering Approach 25%
• Hardware Constraints 25%
• Bandwidth Limitation 25%

Computer Science

• Multi-Objective Optimization 100%
• Field Programmable Gate Arrays 100%
• Optimization Algorithm 100%
• Configurable Logic Block 80%
• clustering approach 20%
• Performance Parameter 20%
• Benchmark Circuit 20%
• Computer Hardware 20%
• Clustering Algorithm 20%
• Achievable Performance 20%
• Computer Aided Design 20%
• multi-objective evolutionary algorithm 20%

Engineering

• Field Programmable Gate Arrays 100%
• Multiobjective Optimization 100%
• Driven Circuit 100%
• Process Route 20%
• Circuit Design 20%
• Multiobjective Genetic Algorithm 20%
• Fundamental Process 20%
• Clustering Algorithm 20%
• Improving Device 20%
• Performance Parameter 20%
• Computer Aided Design 20%
• Circuit Performance 20%
• Interconnects 20%