A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

Nilesh Karavadara, Simon Folie, Michael Zolda, Vu Thien Nga Nguyen, Raimund Kirner

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Downloads (Pure)

Abstract

Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores.
Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network.
We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices.
Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.
Original languageEnglish
Title of host publicationInt'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)
Number of pages4
Publication statusPublished - 1 Mar 2014
EventInt'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems - Dresden, Germany
Duration: 24 Mar 201428 Mar 2014
http://ecsi.org/workshop2014/date/3pmces-agenda

Conference

ConferenceInt'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems
Abbreviated title3PMCES'14
Country/TerritoryGermany
CityDresden
Period24/03/1428/03/14
Internet address

Fingerprint

Dive into the research topics of 'A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip'. Together they form a unique fingerprint.

Cite this