A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

Nilesh Karavadara; Simon Folie; Michael Zolda; Vu Thien Nga Nguyen; Raimund Kirner

A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

Nilesh Karavadara
, Simon Folie
, Michael Zolda
, Vu Thien Nga Nguyen
, Raimund Kirner

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Abstract

Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores.
Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network.
We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices.
Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.

Original language	English
Title of host publication	Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)
Number of pages	4
Publication status	Published - 1 Mar 2014
Event	Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems - Dresden, Germany Duration: 24 Mar 2014 → 28 Mar 2014 http://ecsi.org/workshop2014/date/3pmces-agenda

Conference

Conference	Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems
Abbreviated title	3PMCES'14
Country/Territory	Germany
City	Dresden
Period	24/03/14 → 28/03/14
Internet address	http://ecsi.org/workshop2014/date/3pmces-agenda

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rr_2014_p124_3PMCES14_scc_power_awareLicence: CC BY

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@inproceedings{c400411849424dcfb75b42ccdb206f24,

title = "A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip",

abstract = "Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores. Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network. We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices. Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.",

author = "Nilesh Karavadara and Simon Folie and Michael Zolda and Nguyen, \{Vu Thien Nga\} and Raimund Kirner",

note = "Nilesh Karavadara, Simon Folie, Michael Zolda, Vu Thien Nga Nguyen, Raimund Kirner, 'A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip'. Paper presented at the Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14), Dresden, Germany, 24-28 March 2014.; Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems , 3PMCES'14 ; Conference date: 24-03-2014 Through 28-03-2014",

year = "2014",

month = mar,

day = "1",

language = "English",

booktitle = "Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)",

url = "http://ecsi.org/workshop2014/date/3pmces-agenda",

}

TY - GEN

T1 - A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

AU - Karavadara, Nilesh

AU - Folie, Simon

AU - Zolda, Michael

AU - Nguyen, Vu Thien Nga

AU - Kirner, Raimund

N1 - Nilesh Karavadara, Simon Folie, Michael Zolda, Vu Thien Nga Nguyen, Raimund Kirner, 'A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip'. Paper presented at the Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14), Dresden, Germany, 24-28 March 2014.

PY - 2014/3/1

Y1 - 2014/3/1

N2 - Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores. Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network. We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices. Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.

AB - Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores. Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network. We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices. Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation.

M3 - Conference contribution

BT - Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14)

T2 - Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems

Y2 - 24 March 2014 through 28 March 2014

ER -

A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

Abstract

Conference

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