Abstract
A fully-integrated Sub-GHz low-power transceiver (TRX) for 802.11ah applications is presented. The receiver takes both advantages of Low-IF/Zero-IF architectures while supporting 1/2/8MHz reconfigurable signal bandwidth. A Σ-Δ fractional-N PLL with Class-C VCO is employed to provide the LOs. In order to enhance the power amplifier (PA) back-off efficiency, a Peak-to-Average-Power-Ratio (PAPR) tolerant technique is proposed with the aid of a power control loop to dynamically detect the input signal PAPR and flexibly reconfigures the PA's operation modes. With digitally-assisted self-calibrations for LO leakage and image rejection, the transmitter obtains -51.6dBc LO leakage and 51.2dBc image rejection ratio (IRR). A JESD207 interface is also included to communicate with the digital baseband. Implemented in 180nm CMOS, the receiver achieves 4dB NF and dissipates 18.9mW from a 1.7V supply. The CMOS PA achieves 13.6dBm output P1dB with 25.5% PAE in high power mode (HPM) and ×2.61 PAE improvement at 7dB back-off power in low power mode (LPM).
Original language | English |
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Title of host publication | Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 231-234 |
Number of pages | 4 |
Volume | 2015-November |
ISBN (Electronic) | 9781479976416 |
DOIs | |
Publication status | Published - 25 Nov 2015 |
Event | IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 - Phoenix, United States Duration: 17 May 2015 → 19 May 2015 |
Conference
Conference | IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2015 |
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Country/Territory | United States |
City | Phoenix |
Period | 17/05/15 → 19/05/15 |
Keywords
- 802.11ah
- CMOS
- digital self-calibration
- low-power
- PAPR
- power amplifier
- transceiver