A superscalar architecture to exploit instruction level parallelism

G.B. Steven, B. Christianson, R. Collins, F.L. Steven, R. Potter

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent and which therefore can be issued and executed in parallel at run time. This paper provides an overview of the Hatfield Superscalar Architecture (HSA), a multipleinstruction-issue architecture developed at the University of Hertfordshire to support the development of high-performance instruction schedulers. The long-term objective of the HSA project is to develop the scheduling technology to realise an order of magnitude performance improvement over traditional RISC designs. The paper also presents results from the first HSA instruction scheduler that currently achieves a speedup of over three compared to a classic RISC processor.
Original languageEnglish
Pages (from-to)391-400
Number of pages10
JournalMicroprocessors and Microsystems
Issue number7
Publication statusPublished - 17 Mar 1997


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