TY - GEN
T1 - A unified addition structure for moduli set {2n-1, 2 n,2n+1} based on a novel RNS representation
AU - Timarchi, Somayeh
AU - D.cotofana, Sorin
PY - 2010
Y1 - 2010
N2 - Given that modulo 2n±1 are the most popular moduli in Residue Number Systems (RNS), a large variety of modulo 2n±1 adder designs have been proposed based on different number representations. However, in most of the cases, these encodings do not allow the implementation of a unified adder for all the moduli of the form 2n-1, 2 n, and 2n+1. In this paper, we address the modular addition issue by introducing a new encoding, namely, the storedunibit RNS. Moreover, we demonstrate how the proposed representation can be utilized to derive a unified design for the moduli set {2n-1,2n,2 n+1}. Our approach enables a unified design for the moduli set adders, which opens the possibility to design reliable RNS processors with low hardware redundancy. Moreover, the proposed representation can be utilized in conjunction with any fast state of the art binary adder without requiring any extra hardware for end-around-carry addition.
AB - Given that modulo 2n±1 are the most popular moduli in Residue Number Systems (RNS), a large variety of modulo 2n±1 adder designs have been proposed based on different number representations. However, in most of the cases, these encodings do not allow the implementation of a unified adder for all the moduli of the form 2n-1, 2 n, and 2n+1. In this paper, we address the modular addition issue by introducing a new encoding, namely, the storedunibit RNS. Moreover, we demonstrate how the proposed representation can be utilized to derive a unified design for the moduli set {2n-1,2n,2 n+1}. Our approach enables a unified design for the moduli set adders, which opens the possibility to design reliable RNS processors with low hardware redundancy. Moreover, the proposed representation can be utilized in conjunction with any fast state of the art binary adder without requiring any extra hardware for end-around-carry addition.
UR - http://www.scopus.com/inward/record.url?scp=78650751439&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2010.5647761
DO - 10.1109/ICCD.2010.5647761
M3 - Conference contribution
AN - SCOPUS:78650751439
SN - 9781424489350
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 247
EP - 252
BT - 2010 IEEE International Conference on Computer Design, ICCD 2010
T2 - 28th IEEE International Conference on Computer Design, ICCD 2010
Y2 - 3 October 2010 through 6 October 2010
ER -