A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

Lisheng Chen; Lang Chen; Zeyu Ge; Yichuang Sun; Tara Hamilton; Xi Zhu

doi:10.1109/LMWC.2022.3159529

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

Lisheng Chen, Lang Chen, Zeyu Ge, Yichuang Sun, Tara Hamilton, Xi Zhu

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Abstract

Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.

Original language	English
Number of pages	4
Journal	IEEE Microwave and Wireless Components Letters
Early online date	25 Mar 2022
DOIs	https://doi.org/10.1109/LMWC.2022.3159529
Publication status	E-pub ahead of print - 25 Mar 2022

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© 2022 IEEE -This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/LMWC.2022.3159529
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title = "A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS",

abstract = "Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.",

author = "Lisheng Chen and Lang Chen and Zeyu Ge and Yichuang Sun and Tara Hamilton and Xi Zhu",

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T1 - A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

AU - Chen, Lisheng

AU - Chen, Lang

AU - Ge, Zeyu

AU - Sun, Yichuang

AU - Hamilton, Tara

AU - Zhu, Xi

PY - 2022/3/25

Y1 - 2022/3/25

N2 - Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.

AB - Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.

U2 - 10.1109/LMWC.2022.3159529

DO - 10.1109/LMWC.2022.3159529

M3 - Article

SN - 1531-1309

JO - IEEE Microwave and Wireless Components Letters

JF - IEEE Microwave and Wireless Components Letters

ER -

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

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