Addressing Mechanisms for VLIW and Superscalar Processors

F.L. Steven; R.G. Adams; G.B. Steven; L. Wang; D. Whale

doi:10.1016/0165-6074(93)90060-X

Addressing Mechanisms for VLIW and Superscalar Processors

F.L. Steven, R.G. Adams, G.B. Steven, L. Wang, D. Whale

Centre for Computer Science and Informatics Research

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.

Original language	English
Pages (from-to)	75-78
Journal	Microprocessing and Microprogramming
Volume	39
Issue number	2-5
DOIs	https://doi.org/10.1016/0165-6074(93)90060-X
Publication status	Published - 1993

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title = "Addressing Mechanisms for VLIW and Superscalar Processors",

abstract = "RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.",

author = "F.L. Steven and R.G. Adams and G.B. Steven and L. Wang and D. Whale",

note = "Original article can be found at: http://www.sciencedirect.com/science/journal/01656074 Copyright Elsevier B.V. DOI: 10.1016/0165-6074(93)90060-X [Full text of this article is not available in the UHRA]",

year = "1993",

doi = "10.1016/0165-6074(93)90060-X",

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TY - JOUR

T1 - Addressing Mechanisms for VLIW and Superscalar Processors

AU - Steven, F.L.

AU - Adams, R.G.

AU - Steven, G.B.

AU - Wang, L.

AU - Whale, D.

N1 - Original article can be found at: http://www.sciencedirect.com/science/journal/01656074 Copyright Elsevier B.V. DOI: 10.1016/0165-6074(93)90060-X [Full text of this article is not available in the UHRA]

PY - 1993

Y1 - 1993

N2 - RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.

AB - RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.

U2 - 10.1016/0165-6074(93)90060-X

DO - 10.1016/0165-6074(93)90060-X

M3 - Article

SN - 0165-6074

VL - 39

SP - 75

EP - 78

JO - Microprocessing and Microprogramming

JF - Microprocessing and Microprogramming

IS - 2-5

ER -

Addressing Mechanisms for VLIW and Superscalar Processors

Abstract

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