An efficient power-area-delay modulo 2n-1 multiplier

Somayeh Timarchi

doi:10.1109/CADS.2010.5623593

An efficient power-area-delay modulo 2ⁿ-1 multiplier

Somayeh Timarchi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Carry propagation is a main problem in Residue Number System (RNS) arithmetic. This overhead can be eliminated by using redundant number representations which results in Redundant Residue Number System (RRNS). The RNS which uses Stored-Unibit-Transfer (SUT) encoding (SUT-RNS) has been shown as an efficient encoding for RRNS. In this paper, we first propose a general algorithm for radix-2^h SUT-RNS digit multiplication. Then, we implement an efficient pipeline multiplier which is appropriate for frequent multiplications. The results indicate that the radix-8 SUT-RNS modulo 2 ⁿ-1 multiplier outperforms area and power (energy/operation) of the previous efficient RRNS multipliers. Besides, it reaches the speed of the most high-speed RRNS multiplier.

Original language	English
Title of host publication	Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010
Pages	157-160
Number of pages	4
DOIs	https://doi.org/10.1109/CADS.2010.5623593
Publication status	Published - 2010
Externally published	Yes
Event	15th Computer Society of Iran (CSI) Symposium on Computer Architecture and Digital Systems, CADS 2010 - Tehran, Iran, Islamic Republic of Duration: 23 Sept 2010 → 24 Sept 2010

Publication series

Name	Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010

Conference

Conference	15th Computer Society of Iran (CSI) Symposium on Computer Architecture and Digital Systems, CADS 2010
Country/Territory	Iran, Islamic Republic of
City	Tehran
Period	23/09/10 → 24/09/10

Keywords

Modulo multiplier
Pipeline multiplier
Redundant number system
Residue number system

Access to Document

10.1109/CADS.2010.5623593

Cite this

@inproceedings{0d32a5bdedaa4b1c9b0cf414db1b83c3,

title = "An efficient power-area-delay modulo 2n-1 multiplier",

abstract = "Carry propagation is a main problem in Residue Number System (RNS) arithmetic. This overhead can be eliminated by using redundant number representations which results in Redundant Residue Number System (RRNS). The RNS which uses Stored-Unibit-Transfer (SUT) encoding (SUT-RNS) has been shown as an efficient encoding for RRNS. In this paper, we first propose a general algorithm for radix-2h SUT-RNS digit multiplication. Then, we implement an efficient pipeline multiplier which is appropriate for frequent multiplications. The results indicate that the radix-8 SUT-RNS modulo 2 n-1 multiplier outperforms area and power (energy/operation) of the previous efficient RRNS multipliers. Besides, it reaches the speed of the most high-speed RRNS multiplier.",

keywords = "Modulo multiplier, Pipeline multiplier, Redundant number system, Residue number system",

author = "Somayeh Timarchi",

year = "2010",

doi = "10.1109/CADS.2010.5623593",

language = "English",

isbn = "9781424462698",

series = "Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010",

pages = "157--160",

booktitle = "Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010",

note = "15th Computer Society of Iran (CSI) Symposium on Computer Architecture and Digital Systems, CADS 2010 ; Conference date: 23-09-2010 Through 24-09-2010",

}

Timarchi, S 2010, An efficient power-area-delay modulo 2ⁿ-1 multiplier. in Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010., 5623593, Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010, pp. 157-160, 15th Computer Society of Iran (CSI) Symposium on Computer Architecture and Digital Systems, CADS 2010, Tehran, Iran, Islamic Republic of, 23/09/10. https://doi.org/10.1109/CADS.2010.5623593

An efficient power-area-delay modulo 2ⁿ-1 multiplier. / Timarchi, Somayeh.
Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010. 2010. p. 157-160 5623593 (Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Carry propagation is a main problem in Residue Number System (RNS) arithmetic. This overhead can be eliminated by using redundant number representations which results in Redundant Residue Number System (RRNS). The RNS which uses Stored-Unibit-Transfer (SUT) encoding (SUT-RNS) has been shown as an efficient encoding for RRNS. In this paper, we first propose a general algorithm for radix-2h SUT-RNS digit multiplication. Then, we implement an efficient pipeline multiplier which is appropriate for frequent multiplications. The results indicate that the radix-8 SUT-RNS modulo 2 n-1 multiplier outperforms area and power (energy/operation) of the previous efficient RRNS multipliers. Besides, it reaches the speed of the most high-speed RRNS multiplier.

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