An evaluation of the architectural features of the iHARP processor

Keyphrases

• Instruction per Cycle 100%
• Architectural Features 100%
• Instruction Execution 66%
• Hertfordshire 33%
• RISC Processor 33%
• Data Cache 33%
• Scheduler 33%
• Number of Groups 33%
• Static Scheduling 33%
• Instruction-level Parallelism 33%
• VLIW Processor 33%
• Cache Memory 33%
• Fine-grained Parallelism 33%
• Limited Resources 33%
• Number of Data 33%
• Multiple pipelines 33%

Computer Science

• Instructions per Cycle 100%
• Instruction Execution 66%
• Instruction Issue 66%
• Speed-up 33%
• Instruction-Level Parallelism 33%
• Cache Memory 33%
• Pipelining 33%
• VLIW Processor 33%
• Grained Parallelism 33%