Avoiding timing problems in real-time software

P. Puschner, Raimund Kirner

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
23 Downloads (Pure)

Abstract

To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.
Original languageEnglish
Title of host publicationProcs of IEEE Workshop on Software Technologies for Future Embedded Systems
EditorsT. Nakajima, M.H. Kim
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages75-78
Number of pages4
ISBN (Print)0-7695-1937-7
DOIs
Publication statusPublished - 2003
EventIEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003) - HAKODATE
Duration: 15 May 200316 May 2003

Conference

ConferenceIEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003)
CityHAKODATE
Period15/05/0316/05/03

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