Avoiding timing problems in real-time software

P. Puschner; Raimund Kirner

doi:10.1109/WSTFES.2003.1201365

Avoiding timing problems in real-time software

P. Puschner, Raimund Kirner

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

26 Downloads (Pure)

Abstract

To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.

Original language	English
Title of host publication	Procs of IEEE Workshop on Software Technologies for Future Embedded Systems
Editors	T. Nakajima, M.H. Kim
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	75-78
Number of pages	4
ISBN (Print)	0-7695-1937-7
DOIs	https://doi.org/10.1109/WSTFES.2003.1201365
Publication status	Published - 2003
Event	IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003) - HAKODATE Duration: 15 May 2003 → 16 May 2003

Conference

Conference	IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003)
City	HAKODATE
Period	15/05/03 → 16/05/03

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10.1109/WSTFES.2003.1201365

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“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”
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Cite this

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title = "Avoiding timing problems in real-time software",

abstract = "To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.",

author = "P. Puschner and Raimund Kirner",

note = "“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"} “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”; IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003) ; Conference date: 15-05-2003 Through 16-05-2003",

year = "2003",

doi = "10.1109/WSTFES.2003.1201365",

language = "English",

isbn = "0-7695-1937-7",

pages = "75--78",

editor = "T. Nakajima and M.H. Kim",

booktitle = "Procs of IEEE Workshop on Software Technologies for Future Embedded Systems",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Puschner, P & Kirner, R 2003, Avoiding timing problems in real-time software. in T Nakajima & MH Kim (eds), Procs of IEEE Workshop on Software Technologies for Future Embedded Systems. Institute of Electrical and Electronics Engineers (IEEE), pp. 75-78, IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003), HAKODATE, 15/05/03. https://doi.org/10.1109/WSTFES.2003.1201365

TY - GEN

T1 - Avoiding timing problems in real-time software

AU - Puschner, P.

AU - Kirner, Raimund

N1 - “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”

PY - 2003

Y1 - 2003

N2 - To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.

AB - To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.

U2 - 10.1109/WSTFES.2003.1201365

DO - 10.1109/WSTFES.2003.1201365

M3 - Conference contribution

SN - 0-7695-1937-7

SP - 75

EP - 78

BT - Procs of IEEE Workshop on Software Technologies for Future Embedded Systems

A2 - Nakajima, T.

A2 - Kim, M.H.

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003)

Y2 - 15 May 2003 through 16 May 2003

ER -

Avoiding timing problems in real-time software

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