TY - GEN
T1 - Avoiding timing problems in real-time software
AU - Puschner, P.
AU - Kirner, Raimund
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PY - 2003
Y1 - 2003
N2 - To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.
AB - To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time.
U2 - 10.1109/WSTFES.2003.1201365
DO - 10.1109/WSTFES.2003.1201365
M3 - Conference contribution
SN - 0-7695-1937-7
SP - 75
EP - 78
BT - Procs of IEEE Workshop on Software Technologies for Future Embedded Systems
A2 - Nakajima, T.
A2 - Kim, M.H.
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003)
Y2 - 15 May 2003 through 16 May 2003
ER -