Abstract
In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.
Original language | English |
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Pages (from-to) | 111-123 |
Number of pages | 13 |
Journal | Journal of Electronic Testing: Theory and Applications (JETTA) |
Volume | 30 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2014 |
Keywords
- Clock faults
- Clock test
- High performance microprocessors
- Max delay
- Min delay