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Clock faults induced min and max delay violations
D. Rossi
, M. Omaña
, J. M. Cazeaux
, C. Metra
, T. M. Mak
Research output
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peer-review
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Engineering
Max
100%
Duty Cycle
100%
Product Quality
50%
Correct Operation
50%
Keyphrases
Clock Error
100%
Duty Cycle Variation
50%
Product Quality Level
25%
Product Defects
25%
Dramatic Effect
25%
Defect Levels
25%
Specific Tests
25%
Testing Approaches
25%
Computer Science
Product Quality
100%