Abstract
We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component designs into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align data flow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2D DCT algorithm which is widely used in many video communications applications.
Original language | English |
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Title of host publication | Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 |
Editors | Robert Schreiber, Shuvra Bhattacharyya, Neil Burgess, Michael Schulte |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 7-16 |
Number of pages | 10 |
Volume | 2002-January |
ISBN (Electronic) | 0-7695-1712-9 |
DOIs | |
Publication status | Published - 1 Jan 2002 |
Event | IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 - San Jose, United States Duration: 17 Jul 2002 → 19 Jul 2002 |
Conference
Conference | IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 |
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Country/Territory | United States |
City | San Jose |
Period | 17/07/02 → 19/07/02 |
Keywords
- Algorithm design and analysis
- Data flow computing
- Design methodology
- Discrete cosine transforms
- Embedded system
- Hardware
- Reflection