While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling.
|Title of host publication||In: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||Published - 1997|