Design and simulation of an application specific CMOS image sensor

This paper presents a design and simulation of the voltage mode CMOS image sensor (CIS) for a visual aided system, designed for a pose estimation calculation in the total hip replacement surgeries (THR). Firstly, a new imaging system architecture for the application is proposed in this manuscript then a theoretical analysis is discussed to minimize the factors causing nonlinearity in CIS. Secondly, a simulation for the proposed design is presented to give the performance analysis. The CMOS image sensor comprises a pixel array of size 200x200, which is designed in TSMC 0.18um 1-poly 6-metal standard CMOS process technology with a pixel size of 15um and a fill factor of 60%. Combinational logic with the vertical and horizontal scanning DFF chains have been designed to produce input global control signals and read the output signals generated by each pixel respectively. The simulation results depict the right output signals for each pixel within the respective row and column with the changing input signal. Finally, a complete layout for the proposed design is presented which measures 3mm x 3mm in dimension.