We propose a bridge between two important parallel programming paradigms: data parallelism and communicating sequential processes (CSP). Data parallel pipelined architectures obtained with the Alpha language can be embedded in a control intensive application expressed in CSP-based Handel formalism. The interface is formally defined from the semantics of the languages Alpha and Handel. This work will ease the design of compute intensive applications on FPGAs.
|Title of host publication||System Specification & Design Languages|
|Subtitle of host publication||Best of FDL'02|
|Editors||E. Villar , J. Mermet|
|Publication status||Published - 2003|