Design of Highly Parallel Architectures with Alpha and Handel

Florent  de Dinechin; Manju Manjunathaiah; Tanguy Risset; M.  Spivey

doi:10.1007/0-306-48734-9_24

Design of Highly Parallel Architectures with Alpha and Handel

Florent de Dinechin, Manju Manjunathaiah, Tanguy Risset, M. Spivey

Research output: Chapter in Book/Report/Conference proceeding › Chapter (peer-reviewed) › peer-review

Abstract

We propose a bridge between two important parallel programming paradigms: data parallelism and communicating sequential processes (CSP). Data parallel pipelined architectures obtained with the Alpha language can be embedded in a control intensive application expressed in CSP-based Handel formalism. The interface is formally defined from the semantics of the languages Alpha and Handel. This work will ease the design of compute intensive applications on FPGAs.

Original language	English
Title of host publication	System Specification & Design Languages
Subtitle of host publication	Best of FDL'02
Editors	E. Villar , J. Mermet
Publisher	Springer Nature
Chapter	24
Pages	293-302
Edition	1
ISBN (Electronic)	978-0-306-48734-7
ISBN (Print)	978-1-4020-7414-1
DOIs	https://doi.org/10.1007/0-306-48734-9_24
Publication status	Published - 2003

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Design of Highly Parallel Architectures with Alpha and Handel

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