Fast architecture for decimal digit multiplication

Hadi Valikhani, Somayeh Timarchi, Hadi Tabatabaee Malazi

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


Abstract BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication scheme to accelerate this module. Similar to previous articles, our multiplier includes two parts contained binary multiplier and binary to BCD converter. Our contribution towards these modules can successfully overcome the previous BCD digit multipliers. The results indicate 19% hardware acceleration for the proposed multiplier architecture which is comparable to the best previous techniques in UMC 65 nm CMOS standard cells library hardware implementation. Therefore, the proposed BCD digit multiplier is an appropriate candidate to be utilized in BCD arithmetic units.

Original languageEnglish
Article number2186
Pages (from-to)296-301
Number of pages6
JournalMicroprocessors and Microsystems
Issue number4-5
Publication statusPublished - 31 May 2015


  • Binary and BCD multiplication
  • Binary coded decimal (BCD) encoding
  • Binary to BCD conversion
  • Computer arithmetic


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