Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm

Y. He; Y. Sun

doi:10.1109/ISCAS.2001.922372

Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm

Y. He
, Y. Sun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

105 Downloads (Pure)

Abstract

This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.

Original language	English
Title of host publication	Procs IEEE Int Symposium on Circuits & Systems
Subtitle of host publication	ISCAS 2001
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	854-857
Volume	4
ISBN (Print)	0-7803-6685-9
DOIs	https://doi.org/10.1109/ISCAS.2001.922372
Publication status	Published - 2001

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10.1109/ISCAS.2001.922372

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“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”
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title = "Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm",

abstract = "This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.",

author = "Y. He and Y. Sun",

note = "“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"} “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”",

year = "2001",

doi = "10.1109/ISCAS.2001.922372",

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AU - He, Y.

AU - Sun, Y.

N1 - “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”

PY - 2001

Y1 - 2001

N2 - This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.

AB - This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.

U2 - 10.1109/ISCAS.2001.922372

DO - 10.1109/ISCAS.2001.922372

M3 - Conference contribution

SN - 0-7803-6685-9

VL - 4

SP - 854

EP - 857

BT - Procs IEEE Int Symposium on Circuits & Systems

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm

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