In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.