Fixed pattern noise reduction and linearity improvement in time-mode CMOS image sensors

Miron Kłosowski; Yichuang Sun

doi:10.3390/s20205921

Fixed pattern noise reduction and linearity improvement in time-mode CMOS image sensors

Miron Kłosowski, Yichuang Sun

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Abstract

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.

Original language	English
Article number	5921
Number of pages	16
Journal	Sensors
Volume	20
Issue number	20
DOIs	https://doi.org/10.3390/s20205921
Publication status	Published - 20 Oct 2020

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10.3390/s20205921Licence: CC BY

sensors_20_05921_v2
© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
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@article{77a1061ff6fe40058e072d5e5284e550,

title = "Fixed pattern noise reduction and linearity improvement in time-mode CMOS image sensors",

abstract = "In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.",

author = "Miron K{\l}osowski and Yichuang Sun",

note = "{\textcopyright} 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).",

year = "2020",

month = oct,

day = "20",

doi = "10.3390/s20205921",

language = "English",

volume = "20",

journal = "Sensors",

issn = "1424-3210",

publisher = "MDPI Multidisciplinary Digital Publishing Institute",

number = "20",

}

TY - JOUR

T1 - Fixed pattern noise reduction and linearity improvement in time-mode CMOS image sensors

AU - Kłosowski, Miron

AU - Sun, Yichuang

N1 - © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

PY - 2020/10/20

Y1 - 2020/10/20

N2 - In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.

AB - In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.

U2 - 10.3390/s20205921

DO - 10.3390/s20205921

M3 - Article

SN - 1424-3210

VL - 20

JO - Sensors

JF - Sensors

IS - 20

M1 - 5921

ER -

Fixed pattern noise reduction and linearity improvement in time-mode CMOS image sensors

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