TY - JOUR
T1 - Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2 n-1, 2 n, 2 n+1}
AU - Fazlali, Mahmood
PY - 2012/9
Y1 - 2012/9
N2 - Residue number system (RNS) which utilises redundant encoding for the residues is called redundant residue number system (RRNS). It can accelerate multiplication which is a high-latency operation. Using stored-unibit-transfer (SUT) redundant encoding in RRNS called SUT-RNS has been shown as an efficient number system for arithmetic operation. Radix-2 h SUT-RNS multiplication has been proposed in previous studies for modulo 2 n-1, but it has not been generalised for each moduli lengths (n) and radix (r=2 h). Also, SUT-RNS multiplication for modulo 2n+1 has not been discussed. In this study the authors remove these weaknesses by proposing general radix-2 h SUT-RNS multiplication for the moduli set {2 n-1, 2 n, 2 n+1}. Moreover, the authors demonstrate that our approach enables a unified design for the moduli set multipliers, which results in designing fault-tolerant SUT-RNS multipliers with low hardware redundancy. Results indicate that the proposed general SUT-RNS multiplier for the moduli set {2 n-1, 2 n, 2 n+1} is a fast fault-tolerant multiplier which outperforms area, power and energy/operation of existing RRNS multiplier.
AB - Residue number system (RNS) which utilises redundant encoding for the residues is called redundant residue number system (RRNS). It can accelerate multiplication which is a high-latency operation. Using stored-unibit-transfer (SUT) redundant encoding in RRNS called SUT-RNS has been shown as an efficient number system for arithmetic operation. Radix-2 h SUT-RNS multiplication has been proposed in previous studies for modulo 2 n-1, but it has not been generalised for each moduli lengths (n) and radix (r=2 h). Also, SUT-RNS multiplication for modulo 2n+1 has not been discussed. In this study the authors remove these weaknesses by proposing general radix-2 h SUT-RNS multiplication for the moduli set {2 n-1, 2 n, 2 n+1}. Moreover, the authors demonstrate that our approach enables a unified design for the moduli set multipliers, which results in designing fault-tolerant SUT-RNS multipliers with low hardware redundancy. Results indicate that the proposed general SUT-RNS multiplier for the moduli set {2 n-1, 2 n, 2 n+1} is a fast fault-tolerant multiplier which outperforms area, power and energy/operation of existing RRNS multiplier.
UR - http://www.scopus.com/inward/record.url?scp=84867781549&partnerID=8YFLogxK
U2 - 10.1049/iet-cdt.2011.0075
DO - 10.1049/iet-cdt.2011.0075
M3 - Article
AN - SCOPUS:84867781549
SN - 1751-8601
VL - 6
SP - 269
EP - 276
JO - IET Computers and Digital Techniques
JF - IET Computers and Digital Techniques
IS - 5
ER -