Hades - towards the design of an asynchronous superscalar processor

C.J. Elston, B. Christianson, P. Findlay, G.B. Steven

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Hades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous processor design and demonstrates why it is undesirable to design a processor which is simply an asynchronous version of an existing synchronous processor. Particular emphasis is placed on an explicitly declared delayed branch mechanism and a decoupled register forwarding mechanism developed for Hades. Ths branch mechanism allows instruction fetching to proceed while branch instructions are being resolved, while the forwarding mechanism allows the last result of each functional unit to be bypassed to following instructions, yet completely separates bypassing from the register write back operation.
Original languageEnglish
PublisherUniversity of Hertfordshire
Publication statusPublished - 1995

Publication series

NameUH Computer Science Technical Report
PublisherUniversity of Hertforshire

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