Hades - towards the design of an asynchronous superscalar processor

C.J. Elston; B. Christianson; P. Findlay; G.B. Steven

Hades - towards the design of an asynchronous superscalar processor

C.J. Elston, B. Christianson, P. Findlay, G.B. Steven

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Abstract

Hades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous processor design and demonstrates why it is undesirable to design a processor which is simply an asynchronous version of an existing synchronous processor. Particular emphasis is placed on an explicitly declared delayed branch mechanism and a decoupled register forwarding mechanism developed for Hades. Ths branch mechanism allows instruction fetching to proceed while branch instructions are being resolved, while the forwarding mechanism allows the last result of each functional unit to be bypassed to following instructions, yet completely separates bypassing from the register write back operation.

Original language	English
Publisher	University of Hertfordshire
Publication status	Published - 1995

Publication series

Name	UH Computer Science Technical Report
Publisher	University of Hertforshire
Volume	218

Access to Document

CSTR 218.pdf

Cite this

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abstract = "Hades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous processor design and demonstrates why it is undesirable to design a processor which is simply an asynchronous version of an existing synchronous processor. Particular emphasis is placed on an explicitly declared delayed branch mechanism and a decoupled register forwarding mechanism developed for Hades. Ths branch mechanism allows instruction fetching to proceed while branch instructions are being resolved, while the forwarding mechanism allows the last result of each functional unit to be bypassed to following instructions, yet completely separates bypassing from the register write back operation.",

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T1 - Hades - towards the design of an asynchronous superscalar processor

AU - Elston, C.J.

AU - Christianson, B.

AU - Findlay, P.

AU - Steven, G.B.

PY - 1995

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N2 - Hades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous processor design and demonstrates why it is undesirable to design a processor which is simply an asynchronous version of an existing synchronous processor. Particular emphasis is placed on an explicitly declared delayed branch mechanism and a decoupled register forwarding mechanism developed for Hades. Ths branch mechanism allows instruction fetching to proceed while branch instructions are being resolved, while the forwarding mechanism allows the last result of each functional unit to be bypassed to following instructions, yet completely separates bypassing from the register write back operation.

AB - Hades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous processor design and demonstrates why it is undesirable to design a processor which is simply an asynchronous version of an existing synchronous processor. Particular emphasis is placed on an explicitly declared delayed branch mechanism and a decoupled register forwarding mechanism developed for Hades. Ths branch mechanism allows instruction fetching to proceed while branch instructions are being resolved, while the forwarding mechanism allows the last result of each functional unit to be bypassed to following instructions, yet completely separates bypassing from the register write back operation.