This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in conjunction with a simple compile-time scheduling technique called conditional compaction. The architecture is characterised by a conditional execution mechanism which is used by the scheduler to pack the instructions within a procedure into long instruction words. The study compares the speedups obtained for the C and Modula-2 versions of a set of short, general purpose, integer benchmarks, running on simulations of the architecture with different functional unit configurations.
|Name||UH Computer Science Technical Report|
|Publisher||University of Hertfordshire|