HARP: a VLIW RISC processor

P. Findlay, S.A. Trainis, G.B. Steven, R.G. Adams

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
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Abstract

HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced Instruction Set Computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC type instructions.
Original languageEnglish
Title of host publicationIn: Procs of 5th Annual European Computer Conference, CompEuro'91
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages368-372
ISBN (Print)0-8186-2141-9
DOIs
Publication statusPublished - 1991

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