HARP: a VLIW RISC processor

P. Findlay; S.A. Trainis; G.B. Steven; R.G. Adams

doi:10.1109/CMPEUR.1991.257412

HARP: a VLIW RISC processor

P. Findlay
, S.A. Trainis
, G.B. Steven
, R.G. Adams

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

53 Downloads (Pure)

Abstract

HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced Instruction Set Computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC type instructions.

Original language	English
Title of host publication	In: Procs of 5th Annual European Computer Conference, CompEuro'91
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	368-372
ISBN (Print)	0-8186-2141-9
DOIs	https://doi.org/10.1109/CMPEUR.1991.257412
Publication status	Published - 1991

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title = "HARP: a VLIW RISC processor",

abstract = "HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced Instruction Set Computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC type instructions.",

author = "P. Findlay and S.A. Trainis and G.B. Steven and R.G. Adams",

note = "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. DOI : 10.1109/CMPEUR.1991.257412",

year = "1991",

doi = "10.1109/CMPEUR.1991.257412",

language = "English",

isbn = "0-8186-2141-9",

pages = "368--372",

booktitle = "In: Procs of 5th Annual European Computer Conference, CompEuro'91",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

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AU - Findlay, P.

AU - Trainis, S.A.

AU - Steven, G.B.

AU - Adams, R.G.

N1 - This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. DOI : 10.1109/CMPEUR.1991.257412

PY - 1991

Y1 - 1991

N2 - HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced Instruction Set Computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC type instructions.

AB - HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced Instruction Set Computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC type instructions.

U2 - 10.1109/CMPEUR.1991.257412

DO - 10.1109/CMPEUR.1991.257412

M3 - Conference contribution

SN - 0-8186-2141-9

SP - 368

EP - 372

BT - In: Procs of 5th Annual European Computer Conference, CompEuro'91

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

HARP: a VLIW RISC processor

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