High-Performance Memory Allocation on FPGA with reduced Internal Fragmentation: Memory Allocation on FPGA

Mohamad Mehdi Sadeghi, Somayyeh Timarchi, Mahmood Fazlali

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In this paper, we present two distinct hardware dynamic memory allocation schemes that are based on the binary buddy system algorithm. Our aim is to mitigate internal fragmentation without impacting the area and performance of the system. The first scheme introduces a parallel design for calculating the addresses of free blocks, which results in a decrease in allocation latency while maintaining acceptable resource utilization. This scheme is particularly well-suited for managing a limited number of minimum allocable units (MAU). On the other hand, the second allocator can handle a large number of MAUs due to its innovative searching mechanism. This allocator exhibits lower resource consumption and operates with an acceptable allocation latency. Furthermore, to decrease internal fragmentation, we develop a novel update mechanism for allocating information data structures in both methods. By employing these two allocator schemes, we can improve the efficiency and resource management of dynamic memory allocation for hardware systems. Experimental results demonstrate that the first and second proposed schemes achieve a minimum allocation speed-up of ×2 and ×1.8 compared to their counterparts. At the same time, they achieve a reduction of at least 78% and %88 in resource utilization, respectively. The results show that the total fragmentation is reduced by at least 14% due to the lower internal fragmentation.
Original languageEnglish
Pages (from-to)66672-66681
Number of pages10
JournalIEEE Access
Early online date27 Jun 2023
Publication statusPublished - 7 Jul 2023


  • Dynamic memory allocator
  • Dynamic scheduling
  • Field programmable gate arrays
  • Hardware
  • Heuristic algorithms
  • Memory management
  • Registers
  • Resource management
  • field programmable gate array (FPGA)
  • high-performance
  • internal fragmentation


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