High-performance robust latches

Martin Omaña, Daniele Rossi, Cecilia Metra

    Research output: Contribution to journalArticlepeer-review

    78 Citations (Scopus)


    First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths.

    Original languageEnglish
    Article number5396333
    Pages (from-to)1455-1465
    Number of pages11
    JournalIEEE Transactions on Computers
    Issue number11
    Publication statusPublished - 2010


    • hardened latch
    • robust design
    • soft errors
    • static latch
    • Transient faults


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