High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding

Somayeh Timarchi; Maryam Saremi; Georgi Gaydadjiev

doi:10.1109/VLSI-SoC.2013.6673248

High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding

Somayeh Timarchi, Maryam Saremi, Georgi Gaydadjiev

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.

Original language	English
Title of host publication	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	58-59
Number of pages	2
ISBN (Print)	9781479905249
DOIs	https://doi.org/10.1109/VLSI-SoC.2013.6673248
Publication status	Published - 2013
Externally published	Yes
Event	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey Duration: 7 Oct 2013 → 9 Oct 2013

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
Country/Territory	Turkey
City	Istanbul
Period	7/10/13 → 9/10/13

Keywords

Binary Signed Digit
Carry-Free Addition
Residue Number System

Access to Document

10.1109/VLSI-SoC.2013.6673248

Cite this

Timarchi, S., Saremi, M., & Gaydadjiev, G. (2013). High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings (pp. 58-59). Article 6673248 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/VLSI-SoC.2013.6673248

Timarchi, Somayeh ; Saremi, Maryam ; Gaydadjiev, Georgi. / High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), 2013. pp. 58-59 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

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abstract = "Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.",

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Timarchi, S, Saremi, M & Gaydadjiev, G 2013, High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings., 6673248, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, Institute of Electrical and Electronics Engineers (IEEE), pp. 58-59, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, 7/10/13. https://doi.org/10.1109/VLSI-SoC.2013.6673248

High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. / Timarchi, Somayeh; Saremi, Maryam; Gaydadjiev, Georgi.
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), 2013. p. 58-59 6673248 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.

AB - Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.

KW - Binary Signed Digit

KW - Carry-Free Addition

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Timarchi S, Saremi M, Gaydadjiev G. High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE). 2013. p. 58-59. 6673248. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2013.6673248

High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding

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